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512k x 8 static ram cy62148b cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 document #: 38-05039 rev. *a revised june 19, 2001 features ? 4.5v?5.5v operation ? cmos for optimum speed/power ? low active power ? 165 mw (max.) ? low standby power (l version) ? 110 w (max.) ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe options functional description the cy62148 is a high-performance cmos static ram orga- nized as 524,288 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. this device has an automatic power-down feature that reduces power con- sumption by more than 99% when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location speci- fied on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip en- able (ce ) and output enable (oe ) low while forcing write enable (we ) high for read. under these conditions, the con- tents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy62148 is available in a standard 32-pin 450-mil-wide body width soic and 32-pin tsop ii packages. 18 13 logic block diagram pin configuration a 1 a 4 a 5 a 6 a 7 a 12 a 14 a 16 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512 x 256 x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 2 a 15 a 3 a ce a a 8 a 17 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 12 13 29 32 31 30 16 15 17 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 i/o 0 i/o 1 i/o 2 ce oe a 10 i/o a 1 a 0 a 11 a 9 a 11 a 18 a 10 16 15 14 13 12 11 10 9 8 7 6 3 30 29 25 26 27 28 24 21 22 23 5 4 20 17 18 19 1 2 32 31 a 17 i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 a 3 a 4 a 13 a 18 a 15 a 5 a 12 a 14 a 16 a 8 a 9 v cc a 6 a 7 tsop ii top view soic tsop ii top view reverse gnd gnd i/o 3 i/o 3 i/o 6 i/o 5 i/o 4 i/o 7 ce oe a 10 a 11 a 17 we
cy62148b document #: 38-05039 rev. *a page 2 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65c to +150c ambient temperature with power applied............................................. ?55c to +125c supply voltage on v cc to relative gnd ....... ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] .....................................?0.5v to v cc +0.5v dc input voltage [1] ..................................?0.5v to v cc +0.5v current into outputs (low) ........................................ 20 ma static discharge voltage...............................................2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. selection guide cy62148bll-55 cy62148bll-70 unit max access time 55 70 ns max operating current (i cc ) commercial ll 30 20 ma industrial 30 20 ma max cmos standby current (i sb2) commercial ll 20 20 a industrial 20 20 a operating range range ambient temperature [2] v cc commercial 0c to +70c 4.5v?5.5v industrial ?40c to +85c
cy62148b document #: 38-05039 rev. *a page 3 of 11 electrical characteristics over the operating range parameter description test conditions cy62148b-55 cy62148b-70 unit min. typ. [3] max. min. typ. (3) max v oh output high voltage v cc = min., i oh = ? 1 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 2.1 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 ?0.3 0.8 v i ix input load current gnd v i v cc ?1 +1 ?1 +1 a i oz output leakage current gnd v i v cc , output disabled ?1 + 1 ?1 +1 a i cc v cc operating supply current v cc = max., i out =0 ma, f = f max = 1/t rc ind?l ll 30 20 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce v ih v in v ih or v in v il , f = f max ind?l ll 2.5 1.5 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce v cc ? 0.3v, v in v cc ? 0.3v, or v in 0.3v, f = 0 ind?l ll 4 20 4 20 a i cc v cc operating supply current v cc = max., i out =0 ma, f = f max = 1/t rc com ll 30 20 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce v ih v in v ih or v in v il , f = f ma com ll 2.5 1.5 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce v cc ? 0.3v, v in v cc ? 0.3v, or v in 0.3v, f=0 com ll 4 20 4 20 a capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 6 pf c out output capacitance 8 pf note: 3. typical values are measured at v cc = 5v, t a = 25c, and are included for reference only and are not tested or guaranteed. 4. tested initially and after any design or process changes that may affect these parameters.
cy62148b document #: 38-05039 rev. *a page 4 of 11 ac test loads and waveforms switching characteristics [5] over the operating range cy62148bll-55 62148bll?70 parameter description min. max. min. max. unit read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [6] 5 5 ns t hzoe oe high to high z [6, 7] 20 25 ns t lzce ce low to low z [6] 10 10 ns t hzce ce high to high z [6, 7] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 55 70 ns write cycle [8] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 45 55 ns t sd data set-up to write end 30 30 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [6] 5 5 ns t hzwe we low to high z [6, 7] 20 25 ns notes: 5. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 100-pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 8. the internal write time of the memory is defined by the overlap of ce 1 low, and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 5v output 5 pf including jig and scope (b) r2 990 ? (a) 90% 10% 5.0v gnd 90% 10% 3 ns 3ns output 639 ? equivalent to: thevenin equivalent 1.77v r1 1800 ? all input pulses 5v output including jig and scope r2 990 ? r1 1800 ? 100 pf
cy62148b document #: 38-05039 rev. *a page 5 of 11 data retention characteristics (over the operating range) parameter description conditions min. typ. [2] max. unit v dr v cc for data retention 2.0 v i ccdr data retention current com?l ll no input may exceed v cc + 0.3v v cc = v dr = 3.0v ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 20 a ind?l ll 20 a t cdr [4] chip deselect to data retention time 0 ns t r operation recovery time t rc ns data retention waveform switching waveforms read cycle no.1 [9, 10] read cycle no. 2 (oe controlled) [10, 11] notes: 9. device is continuously selected. oe , ce = v il . 10. we is high for read cycle. 11. address valid prior to or coincident with ce transition low. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i sb impedance address data out v cc supply current
cy62148b document #: 38-05039 rev. *a page 6 of 11 write cycle no. 1 (ce controlled) [12] write cycle no. 2 (we controlled, oe high during write) [12, 13] notes: 12. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 13. data i/o is high-impedance if oe = v ih . 14. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 14
cy62148b document #: 38-05039 rev. *a page 7 of 11 write cycle no.3 (we controlled, oe low) [12, 13] truth table ce oe we i/o 0 ? i/o 7 mode power h x x high z power-down standby (i sb ) l l h data out read standby (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 14 ordering information speed (ns) ordering code package name package type operating range 70 cy62148bll-70sc s34 32-lead (450-mil) molded soic commercial cy62148bll-70zc zs32 32-lead tsop ii cy62148bll-70zrc zu32 32-lead rtsop ii cy62148bll-70si s34 32-lead (450-mil) molded soic industrial cy62148bll-70zi zs32 32-lead tsop ii cy62148bll-70zri zu32 32-lead rtsop ii 55 cy62148bll-55sc s34 32-lead (450-mil) molded soic commercial cy62148bll-55zc zs32 32-lead tsop ii cy62148bll-55zrc zu3s 32-lead rtsop ii cy62148bll-55si s34 32-lead (450-mil) molded soic industrial cy62148bll-55zi zs32 32-lead tsop ii CY62148BLL-55ZRI zu32 32-lead rtsop ii
cy62148b document #: 38-05039 rev. *a page 8 of 11 package diagrams 32-lead (450 mil) molded soic s34 51-85081-a
cy62148b document #: 38-05039 rev. *a page 9 of 11 package diagrams (continued) 32-lead tsop ii zs32 51-85095
cy62148b document #: 38-05039 rev. *a page 10 of 11 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 51-85138-** 32-lead reverse thin small outline package type ii zu32
cy62148b document #: 38-05039 rev. *a page 11 of 11 document title: cy62148b 512k x 8 static ram document number: 38-05039 rev. ecn no. issue date orig. of change description of change ** 106833 05/01/01 szv change from spec number 38-01104 to 38-05039 *a 106970 07/16/01 gav modified annotations on pin configurations; t sd = 30 ns

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